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How Chips Are Using On-Chip Strain to Boost Performance

How Chips Are Using On-Chip Strain to Boost Performance

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In this episode of The Hardware Podcast, Lucas and Luna explore the technique of applying mechanical strain to silicon transistors to improve electron mobility, a method chipmakers like Intel and TSMC have used since the 90nm node. Lucas explains the physics behind strained silicon, how uniaxial strain differs from biaxial, and why it's still relevant at 3nm and beyond. Luna brings in a specific example: how Intel's 45nm 'Hi-K + Metal Gate' combined strain with high-k dielectrics for a 20% performance boost. They discuss the manufacturing challenges, the shift to process-induced strain like embedded SiGe and stress liners, and whether strain engineering will survive the transition to gate-all-around transistors. A concrete look at a quiet but critical enabler of modern chip performance. #StrainedSilicon #ChipEngineering #ElectronMobility #Intel #TSMC #SemiconductorPhysics #HiKMetalGate #SiGe #StressLiners #UniaxialStrain #FinFET #GateAllAround #NanometerNodes #ProcessTechnology #Technology #HardwarePodcast #FexingoBusiness #BusinessPodcast Keep every episode free: buymeacoffee.com/fexingo
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